MyLogic Station^TM V5.1 is the schematic capture with logic-level simulator solution to provide easy to use and cost effective way of making prototypes. MyLogic Station^TM V5.1 enables FPGA design by generating schematic netlist to structural VHDL or EDIF netlist. And it accepts VHDL codes or EDIF to generate the schematic data.

To obtain a Brochure of MyLogic Station^TM V5.1, Please click here.
To obtain a GUI of MyLogic Station^TM V5.1, Please click here.
To obtain a Job Flow of MyLogic Station^TM V5.1, Please click here.

MyLogic Station^TM V5.1 Highlight

 

Schematic Editor

Logic Simulator

Schematic Editor   

• Supports on-line circuit check.

• Structural VHDL generation .

• Boolean Equation.

• Schematic generation from EDIF netlist.

• State Diagram Editor.

• EDIF netlist generation .

Logic Simulator   

• Logic level simulator.

• Supports typing commands.

• Waveform Analyzer.

• Easy to draw waveform for stimulus.

• Test bench generation for VHDL simulation.

Please click here if you want to download MyLogic Station^TM V5.1