MyChip Station^TM Pro is a sophisticated physical design system, which can turn a Windows based personal computer into a powerful engineering workstation.
At the forefront of MyChip Station Pro is LayEdPro, a polygon based, full custom IC layout editor featuring a user customizable environment.
Physical design verification is accomplished using the design rule checker, MyDRCPro, and the layout versus schematic comparison tool, MyLVSPro. Next, the netlist extraction tool, LayNetPro, can extract parasitic information for use in post layout circuit simulations.
 These verification tools operate using user definable run files that are similar to and somewhat compatible with, DRACULA^TM.
CifGDSPro enables the user to import and export layout data using industry standard GDS, CIF and DXF formats.

• LayEd Pro (Layout Editor)
• MyDRC Pro (Design Rule Checker)
• LayNet Pro(Electrical Rule Checker)
• MyLVS Pro(Layout Versus Schematic)
• CIFGDS Pro(Data Converter)

   LayEd Pro (Layout Editor)   

LayEdPro is a powerful and versatile polygon based layout editor using the familiar MS Windows graphical user interface. LayEdPro has all the features that professional users have come to expect, including dynamic display speed, hierarchical multi-window editing and automated system recovery capability.

Main Feature

Hierarchical layout design
• View layout details down to any level of the hierarchy
• Provide Edit-in-place command to edit directly any object   in the hierarchy

User Programmable Interface
Support Visual Basic Script for designing complex patterns such as spiral

Real-Time DRC
Real-Time DRC provides real-time display of DRC violations while editing a layout. It supports width, length, space, enclosing, extension, overlap rules, and there is no limit to the number of rules.

Boolean Operation
• Cell operation command for performing Boolean edits on   cells
• Layer operation command for performing Boolean edits on   layers
• Add, Intersect, Merge, Punch, Subtract commands for   performing operations on objects

Journaling and Macro
Journalizing capability allows design engineers to access a complete journal of all the commands executed in case of System crashing for some reason. By executing the file, the program automatically regenerates the layout saving the design engineers precious work.

Mark Net
Mark Net enables design engineers to trace the physical connectivity of a net in a layout design without generating a SPICE netlist.

Reshape a corner
Provide Fillet and Octbias commands to reshape the corner of polygon to make a rounded or chamfered edge

Command line interface
• Display message and warning
• Enter commands

Customizable bind keys and toolbars
Provide bind keys and toolbars editor

Unlimited undo/redo
User configurable undo/redo level

Powerful editing commands
• Stretch objects
• Edit edge or vertex
• Enlarge or reduce objects Technology File Editor
• Create and edit design layers Layer Manager
• Make layers visible or invisible/ select or unselect

   MyDRC Pro(Hierarchical Design Rule Checker)   

   LayNet Pro (Hierarchical SPICE Netlist Extractor & Electrical Rule Checker)

   MyLVS Pro (Hierarchical Layout Versus Schematic)    

   CIFGDS Pro(Data Converter)